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1 mx25l8073e high performance serial flash specification mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
2 contents 1. features ........................................................................................................................................................ 4 2. general description ............................................................................................................................... 6 table 1. additional feature ..................................................................................................................... 6 3. pin configuration ...................................................................................................................................... 7 4. pin description ............................................................................................................................................ 7 5. block diagram ............................................................................................................................................. 8 6. data protection .......................................................................................................................................... 9 table 2. protected area sizes .............................................................................................................. 10 table 3. 4k-bit secured otp defnition ............................................................................................... 10 7. memory organization .............................................................................................................................. 11 table 4. memory organization ............................................................................................................. 11 8. device operation ...................................................................................................................................... 12 9. command description ............................................................................................................................. 13 table 5. command sets ....................................................................................................................... 13 9-1. write enable (wren) .......................................................................................................................... 15 9-2. write disable (wrdi) ........................................................................................................................... 16 9-3. read identifcation (rdid) ................................................................................................................... 17 9-4. read status register (rdsr) ............................................................................................................. 18 9-5. write status register (wrsr) ............................................................................................................. 20 table 6. protection modes .................................................................................................................... 21 9-6. read data bytes (read) .................................................................................................................... 23 9-7. read data bytes at higher speed (fast_read) .............................................................................. 24 9-8. dual read mode (dread) .................................................................................................................. 25 9-9. 2 x i/o read mode (2read) ............................................................................................................... 26 9-10. quad read mode (qread) ................................................................................................................ 27 9-11. 4 x i/o read mode (4read) ............................................................................................................... 28 9-12. performance enhance mode ............................................................................................................... 29 9-13. performance enhance mode reset (ffh) ........................................................................................... 31 9-14. sector erase (se) ................................................................................................................................ 32 9-15. block erase (be) ................................................................................................................................. 33 9-16. chip erase (ce) ................................................................................................................................... 34 9-17. page program (pp) ............................................................................................................................. 35 9-18. 4 x i/o page program (4pp) ................................................................................................................ 36 9-19. deep power-down (dp) ....................................................................................................................... 37 9-20. release from deep power-down (rdp), read electronic signature (res) ....................................... 38 9-21. read electronic manufacturer id & device id (rems), (rems2), (rems4) ..................................... 40 9-22. id read ................................................................................................................................................ 41 table 7. id defnitions ......................................................................................................................... 41 9-23. enter secured otp (enso) ................................................................................................................ 41 9-24. exit secured otp (exso) ................................................................................................................... 41 9-25. read security register (rdscur) ..................................................................................................... 42 table 8. security register defnition .................................................................................................... 42 9-26. write security register (wrscur) ..................................................................................................... 43 9-27. read sfdp mode (rdsfdp) .............................................................................................................. 44 table 9. signature and parameter identifcation data values ............................................................. 45 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
3 table 10. parameter table (0): jedec flash parameter tables ......................................................... 46 table 11. parameter table (1): macronix flash parameter tables ....................................................... 48 10. power-on state ....................................................................................................................................... 50 11. electrical specifications .................................................................................................................. 51 11-1. absolute maximum ratings ................................................................................................................. 51 11-2. capacitance ......................................................................................................................................... 51 table 12. dc characteristics ................................................................................................................ 53 table 13. ac characteristics ................................................................................................................ 54 12. timing analysis ........................................................................................................................................ 55 table 14. power-up timing ................................................................................................................. 56 12-1. initial delivery state ............................................................................................................................. 56 13. operating conditions ........................................................................................................................... 57 14. erase and programming performance ........................................................................................ 59 15. data retention ........................................................................................................................................ 59 16. latch-up characteristics .................................................................................................................. 59 17. ordering information .......................................................................................................................... 60 18. part name description ......................................................................................................................... 61 19. revision history ..................................................................................................................................... 63 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
4 8m-bit [x 1/x 2/x 4] cmos mxsmio ? (serial multi i/o) flash memory 1. features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 8m:8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two i/o read mode) structure or 2,097,152 x 4 bits (four i/o read mode) structure ? 256 equal sectors with 4k byte each - any sector can be erased individually ? 16 equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v ? permanent fxed qe bit, qe =1 and 4 i/o mode is enabled performance ? high performance vcc = 2.7~3.6v - normal read - 50mhz - fast read - 1 i/o: 108mhz with 8 dummy cycles - 2 i/o: 80mhz (2.7v~3.6v) ; 104mhz (3.0v~3.6v) with 4 dummy cycles - 4 i/o: 108mhz with 6 dummy cycles - fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page) - byte program time: 9us (typical) - fast erase time: 60ms (typ.)/sector (4k-byte per sector) ; 0.4s(typ.) /block (64k-byte per block); 3s(typ.) /chip ? low power consumption - low active read current: 25ma(max.) at 108mhz, and 10ma(max.) at 50mhz - low active programming current: 20ma (max.) - low active erase current: 20ma (max.) - low standby current: 20ua (typ.) ; 50ua (max.) - deep power-down current: 3ua (typ.) ; 20ua (max.) ? minimum 100,000 erase/program cycles ? 20 years data retention mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
5 software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defnes the size of the area to be software protection against program and erase instructions - additional 4k-bit secured otp for unique identifer ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) ? status register feature ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - all rems,rems2 and rems4 commands for 1-byte manufacturer id and 1-byte device id ? support serial flash discoverable parameters (sfdp) mode hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? sio2 - serial data input/output for 4 x i/o read mode ? sio3 - serial data input/output for 4 x i/o read mode ? package - 8-pin sop (200mil) - all devices are rohs compliant mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
6 2. general description the mx25l8073e are 8,388,608 bit serial flash memory, which is confgured as 1,048,576 x 8 internally. when it is in two or four i/o read mode, the structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. the mx25l8073e feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. when it is in four i/o read mode, the si pin, so pin become sio0 pin and sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data input/output. the mx25l8073e provides sequential read operation on whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci - fed page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, and erase command is executes on sector (4k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. secured otp and block protection, please see security feature and write status register section for more details. when the device is not in operation and cs# is high, it is put in standby mode and draws less than 100ua dc cur - rent. the mx25l8073e utilizes macronix 's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. table 1. additional feature additional features part name protection and security read performance identifer flexible block protection (bp0-bp3) 4k-bit secured otp 2 i/o read 4 i/o read res (command: ab hex) rems (command: 90 hex) rems2 (command: ef hex) rems4 (command: df hex) rdid (command: 9f hex) mx25l8073e v v v v 13 (hex) c2 13 (hex) (if add=0) c2 13 (hex) (if add=0) c2 13 (hex) (if add=0) c2 20 14 (hex) mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
7 3. pin configuration 4. pin description 8-pin sop (200mil) 1 2 3 4 cs# so/sio1 sio2 gnd vcc sio3 sclk si/sio0 8 7 6 5 symbol description cs# chip select si/sio0 serial data input (for 1 x i/o) / serial data input & output (for 2xi/o or 4xi/o read mode) so/sio1 serial data output (for 1 x i/o) serial data input & output (for 2xi/o or 4xi/o read mode) sclk clock input sio2 serial data input & output (for 4xi/o read mode) sio3 serial data input & output (for 4xi/o read mode) vcc + 3.3v power supply gnd ground mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
8 5. block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# sio2 sio3 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
9 6. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or pro - gramming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register ar - chitecture of the device constrains that the memory contents can only be changed after specifc command sequenc - es have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - page program (4pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) command completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic sig - nature command (res). ? advanced security features: there are some protection and security features which protect content from inad - vertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area defnition is shown as table of "protected area sizes", the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of "protected area sizes". mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
10 table 2. protected area sizes status bit protect level bp3 bp2 bp1 bp0 8mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, 1/16 area, block#15) 0 0 1 0 2 (2blocks, 1/8 area, block#14-15) 0 0 1 1 3 (4blocks, 1/4 area, block#12-15) 0 1 0 0 4 (8blocks, 1/2 area, block#8-15) 0 1 0 1 5 (16blocks, all) 0 1 1 0 6 (16blocks, all) 0 1 1 1 7 (16blocks, all) 1 0 0 0 8 (16blocks, all) 1 0 0 1 9 (16blocks, all) 1 0 1 0 10 (16blocks, all) 1 0 1 1 11 (8blocks, 1/2 area, block#0-7) 1 1 0 0 12 (12blocks, 3/4 area, block#0-11) 1 1 0 1 13 (14blocks, 7/8 area, block#0-13) 1 1 1 0 14 (15block, 15/16 area, block#0-14) 1 1 1 1 15 (16blocks, all) ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting device unique serial number - which may be set by factory or system maker. please refer to table 3. 4k-bit secured otp defnition. - security register bit 0 indicates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "security register defnition" for security register bit defnition and table of "4k-bit secured otp defnition" for address range defnition. - note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 4k-bit se - cured otp mode, array access is not allowed. table 3. 4k-bit secured otp defnition address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
11 table 4. memory organization 7. memory organization block sector address range 15 255 0ff000h 0fffffh : : : 240 0f0000h 0f0fffh 14 239 0ef000h 0effffh : : : 224 0e0000h 0e0fffh 13 223 0df000h 0dffffh : : : 208 0d0000h 0d0fffh 12 207 0cf000h 0cffffh : : : 192 0c0000h 0c0fffh 11 191 0bf000h 0bffffh : : : 176 0b0000h 0b0fffh 10 175 0af000h 0affffh : : : 160 0a0000h 0a0fffh 9 159 09f000h 09ffffh : : : 144 090000h 090fffh 8 143 08f000h 08ffffh : : : 128 080000h 080fffh 7 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 15 00f000h 00ffffh : : : 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
12 8. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended opera - tion. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. for standard single data rate serial mode, input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as "figure 1. serial modes supported (for normal serial mode)" . 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, rdsfdp, 2read, dread, 4read, qread, res, rems, rems2 and rems4 the shifted-in instruction sequence is followed by a data- out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, 4pp, cp, rdp, dp, enso, exso, and wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglect - ed and not affect the current operation of write status register, program, erase. note: cpol indicates clock polarity of serial master, -cpol=1 for sclk high while idle, -cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. figure 1. serial modes supported (for normal serial mode) sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
13 9. command description table 5. command sets command (byte) read (read data) fast read (fast read data) rdsfdp (read sfdp) 2read (2 x i/o read command) dread (1i / 2o read command) 4read (4 x i/o read command) qread (1i / 4o read command) 1st byte 03 (hex) 0b (hex) 5a (hex) bb (hex) 3b (hex) eb (hex) 6b (hex) 2nd byte ad1 (a23-a16) ad1 ad1 add ad1 add & dummy ad1 3rd byte ad2 (a15-a8) ad2 ad2 add & dummy ad2 dummy ad2 4th byte ad3 (a7-a0) ad3 ad3 ad3 ad3 5th byte dummy dummy dummy dummy action n bytes read out until cs# goes high n bytes read out until cs# goes high read sfdp mode n bytes read out by 2 x i/o until cs# goes high n bytes read out by 4 x i/o until cs# goes high read commands mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
14 command (byte) be (block erase) ce (chip erase) pp (page program) dp (deep power down) rdp (release from deep power down) res (read electronic id) release read enhanced 1st byte d8 (hex) 60 or c7 (hex) 02 (hex) b9 (hex) ab (hex) ab (hex) ffh (hex) 2nd byte ad1 ad1 x x 3rd byte ad2 ad2 x x 4th byte ad3 ad3 x x action to erase the selected block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode to read out 1-byte device id all these commands ffh, 00h, aah or 55h will escape the performance enhance mode command (byte) rems (read electronic manufacturer & device id) rems2 (read id for 2x i/o mode) rems4 (read id for 4x i/o mode) enso (enter secured otp) exso (exit secured otp) rdscur (read security register) wrscur (write security register) 1st byte 90 (hex) ef (hex) df (hex) b1 (hex) c1 (hex) 2b (hex) 2f (hex) 2nd byte x x x 3rd byte x x x 4th byte add (note3) add (note3) add (note3) action output the manufacturer id & device id output the manufacturer id & device id output the manufacturer id & device id to enter the 512-bit secured otp mode to exit the 512- bit secured otp mode to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be update) note 3: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 4: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hid - den mode. other commands command (byte) wren (write enable) wrdi (write disable) rdid (read identifc- ation) rdsr (read status register) wrsr (write status register) 4pp (quad page program) se (sector erase) 1st byte 06 (hex) 04 (hex) 9f (hex) 05 (hex) 01 (hex) 38 (hex) 20 (hex) 2nd byte values ad1 ad1 3rd byte ad2 4th byte ad3 action sets the (wel) write enable latch bit resets the (wel) write enable latch bit outputs jedec id: 1-byte manufact-urer id & 2-byte device id to read out the values of the status register to write new values of the status register quad input to program the selected page to erase the selected sector mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
15 9-1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low sending wren instruction code cs# goes high. the sio[3:1] are don't care in this mode. figure 2. write enable (wren) sequence (command 06) 2 1 34567 high-z 0 06 command sclk si cs# so mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
16 9-2. write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low sending wrdi instruction code cs# goes high. the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp, 4pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion figure 3. write disable (wrdi) sequence (command 04) 2 1 34567 high-z 0 04 command sclk si cs# so mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
17 figure 4. read identifcation (rdid) sequence (command 9f) 9-3. read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id is c2(hex), the memory type id is as the frst-byte device id, and the individual device id of sec - ond-byte id are listed as table of "table 7. id defnitions" . the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code 24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. 2 1 3456789 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
18 9-4. read status register (rdsr) the rdsr instruction is for reading status register. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. figure 5. read status register (rdsr) sequence (command 05) 2 1 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
19 the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to "1", which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. the program/erase command will be ignored and will reset wel bit if it is applied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrm to be 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in "table 2. protected area sizes" ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase (ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default. which is un-protected. qe bit. the quad enable (qe) bit, a non-volatile bit which is permanently set to "1". the fash always performs quad i/o mode. srwd bit. the status register write disable (srwd) bit, non-volatile bit, default value is "0". status register note: see the "table 2. protected area sizes" . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 0=status register write enable 1= quad enable (note) (note) (note) (note) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
20 9-5. write status register (wrsr) the wrsr instruction is for changing the values of status register bits and confguration register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the protected area of memory (as shown in "table 2. protected area sizes" ). the wrsr can re - set the status register write disable (srwd) bit, but has no effect on bit1 (wel) and bit0 (wip) of the status regis - ter. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on si cs# goes high. figure 6. write status register (wrsr) sequence (command 01) 2 1 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01 high-z command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
21 the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. note: as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in "table 2. protected area sizes" . mode status register condition srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed srwd bit=0 the protected area cannot be programmed or erased. table 6. protection modes software protected mode (spm): - when srwd bit=0, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
22 figure 7. wrsr fow w ren c o mma n d w rsr co mma n d write status register d a t a rdsr co mma n d w rsr succ ess fully yes yes w rs r fa i l n o star t ver ify ok? w ip =0 ? n o rdsr co mma n d yes wel=1 ? n o rdsr co mma n d read w el=0, b p[3:0] , q e, and srwd data mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
23 9-6. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low sending read instruction code3-byte address on si data out on so to end read operation can use cs# to high at any time during data out. figure 8. read data bytes (read) sequence (command 03) sclk si cs# so 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
24 9-7. read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si1-dummy byte (default) address on si data out on so to end fast_read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. figure 9. read at higher speed (fast_read) sequence (command 0b) 23 2 1 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0bh command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
25 9-8. dual read mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on ris - ing edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruction. the address counter rolls over to 0 when the highest address has been reached. once writ - ing dread instruction, the following data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing dread instruction is: cs# goes low sending dread instruction 3-byte address on si 8-bit dummy cycle data out interleave on so1 & so0 to end dread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, dread instruction is rejected without any im - pact on the program/erase/write status register current cycle. figure 10. dual read mode sequence (command 3b) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 30 31 32 39 40 41 43 44 45 42 3b d4 d5 d2 d3 d7 d6 d6 d4 d0 d7 d5 d1 command 24 add cycle 8 dummy cycle a23 a22 a1 a0 data out 1 data out 2 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
26 9-9. 2 x i/o read mode (2read) the 2read instruction enables double transfer rate of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruc - tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address in - terleave on sio1 & sio0 4-bit dummy cycles on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 11. 2 x i/o read mode sequence (command bb) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 18 19 20 bb(hex) p2 p0 address bit22, bit20, bit18...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... address bit23, bit21, bit19...bit1 21 22 23 24 25 26 27 p3 p1 8 bit instruction 12 bit address 4 dummy cycle data output note: si/sio0 or so/sio1 should be kept "0h" or "fh" in the frst two dummy cycles. in other words, p2=p0 or p3=p1 is necessary. mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
27 9-10. quad read mode (qread) the qread instruction enable quad throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single qread instruction. the address counter rolls over to 0 when the highest address has been reached. once writ - ing qread instruction, the following data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing qread instruction is: cs# goes low sending qread instruction 3-byte address on si 8-bit dummy cycle data out interleave on so3, so2, so1 & so0 to end qread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, qread instruction is rejected without any im - pact on the program/erase/write status register current cycle. figure 12. quad read mode sequence (command 6b) high impedance 2 1 345678 0 sclk si/so0 so/so1 cs# 29 9 30 31 32 33 38 39 40 41 42 6b high impedance so2 high impedance so3 8 dummy cycles d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d5 d6 d7 a23 a22 a2 a1 a0 command 24 add cycles data out 1 data out 2 data out 3 ? ? ? mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
28 9-11. 4 x i/o read mode (4read) the 4read instruction enables quad throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruc - tion, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address inter - leave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. figure 13. 4 x i/o read mode sequence (command eb) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 12 10 11 13 14 eb(hex) address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 17 18 19 20 21 22 23 n high impedance sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output note: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) is inhibited. mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
29 another sequence of issuing 4read instruction especially useful in random access is : cs# goes low sending 4read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out until cs# goes high cs# goes low (reduce 4 read instruction) 24-bit ran - dom access address (please refer to "figure 14. 4 x i/o read enhance performance mode sequence (command eb)" ). in the performance-enhancing mode (notes of "figure 14. 4 x i/o read enhance performance mode sequence (command eb)" ), p[7:4] must be toggling with p[3:0]; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh, 00h, aah or 55h. these commands will reset the performance enhance mode. and afterwards cs# is raised and then lowered, the system then will return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. 9-12. performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. please be noticed that ebh commands support enhance mode. the performance enhance mode is not supported in dual i/o mode. after entering enhance mode, following csb go high, the device will stay in the read mode and treat csb go low of the frst clock as address instead of command cycle. to exit enhance mode, a new fast read command whose frst two dummy cycles is not toggle then exit. or issue ffh command to exit enhance mode. mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
30 figure 14. 4 x i/o read enhance performance mode sequence (command eb) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 12 10 11 13 14 eb(hex) address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 23 n high impedance sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output sclk note: performance enhance mode, if p7=p3 & p6=p2 & p5=p1 & p4=p0 (toggling), ex: a5, 5a, 0f reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff si/sio0 so/sio1 cs# address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 6 address cycles 4 dummy cycles performance enhance indicator (note) data output note: 1. performance enhance mode, if p7p3 & p6p2 & p5p1 & p4p0 (toggling), ex: a5, 5a, 0f, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
31 figure 15. performance enhance mode reset for fast read quad i/o 2 1 34567 mode 3 don?t care don?t care don?t care mode mode 3 mode sclk io0 cs# io1 ffh io2 io3 mode bit reset for quad i/o 9-13. performance enhance mode reset (ffh) to conduct the performance enhance mode reset operation, ffh command code, 8 clocks, should be issued in 1i/ o sequence. if the system controller is being reset during operation, the fash device will return to the standard operation. upon reset of main chip, instruction would be issued from the system. instructions like read id (9fh) or fast read (0bh) would be issued. the sio[3:1] are don't care when during this mode. mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
32 9-14. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see "table 4. memory organization" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. the sio[3:1] are don't care when during this mode. the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be checked out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the page. figure 16. sector erase (se) sequence (command 20) 24 bit address 2 1 3456789 29 30 31 0 7 6 2 1 0 msb sclk cs# si 20 command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
33 9-15. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see "table 4. memory organization" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. the sio[3:1] are don't care when during this mode. the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be checked out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the page. figure 17. block erase (be) sequence (command d8) 24 bit address 2 1 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8 command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
34 9-16. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low sending ce instruction code cs# goes high. the sio[3:1] are don't care when during this mode. the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be checked out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected, the chip erase (ce) instruction will not be executed, but wel will be reset. figure 18. chip erase (ce) sequence (command 60 or c7) 2 1 34567 0 60 or c7 sclk si cs# command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
35 9-17. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3~0, the array data will be protected (no change) and the wel bit will still be reset. the sio[3:1] are don't care when during this mode. figure 19. page program (pp) sequence (command 02) 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
36 9-18. 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit. the quad page programming takes four pins: sio0, sio1, sio2, and sio3, which can raise programmer performance and the effectiveness of application of lower clock less than f4pp. for system with faster clock, the quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data fows in. therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to f4pp below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0] cs# goes high. if the page is protected by bp3~0, the array data will be protected (no change) and the wel bit will still be reset. figure 20. 4 x i/o page program (4pp) sequence (command 38) 20 21 17 16 12 8 4 0 13 9 5 1 4 4 4 4 0 0 0 0 5 5 5 5 1 1 1 1 2 1 3456789 6 address cycle data byte 1 data byte 2 data byte 3 data byte 4 0 22 18 14 10 6 2 23 19 15 11 7 3 6 6 6 6 2 2 2 2 7 7 7 7 3 3 3 3 sclk cs# si/sio0 so/sio1 sio3 sio2 38 command 10 11 12 13 14 15 16 17 18 19 20 21 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
37 9-19. deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not ac - tive and all write/program/erase instructions are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes low sending dp instruction code cs# goes high. the sio[3:1] are don't care when during this mode. once the dp instruction is set, all instructions will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code has been latched-in); otherwise, the instruction will not be executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. figure 21. deep power-down (dp) sequence (command b9) 2 1 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
38 9-20. release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the standby power mode. if the device was not previously in the deep power-down mode, the transition to the standby power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in "table 13. ac characteristics" . once in the stand - by mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as "table 7. id defnitions" . this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current pro - gram/erase/write cycles in progress. the sio[3:1] are don't care when during this mode. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can receive, decode, and execute instruction. the rdp instruction is for releasing from deep power-down mode. figure 22. release from deep power-down and read electronic signature (res) sequence (command ab) 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 765432 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so abh command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
39 2 1 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command figure 23. release from deep power-down (rdp) sequence (command ab) mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
40 9-21. read electronic manufacturer id & device id (rems), (rems2), (rems4) the rems, rems2, and rems4 instruction provides both the jedec assigned manufacturer id and the specifc device id. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h", "dfh" or "efh" followed by two dummy bytes and one byte address (a7~a0). after which, the manufacturer id for macronix (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in the fgure be - low. the device id values are listed in "table 7. id defnitions" . if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. figure 24. read electronic manufacturer & device id (rems) sequence (command 90 or ef or df) notes: 1. a0=0 will output the manufacturer id frst and a0=1 will output device id frst. a1~a23 are don't care. 2. instruction is either 90(hex) or ef(hex) or df(hex). 2 1 3456789 10 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 manufacturer id msb device id msb msb 47 35 sclk si cs# so 90 high-z command 24 add cycles a23 a22 a21 a2 a3 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 31 30 28 29 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
41 9-22. id read user can execute this id read instruction to identify the device id and manufacturer id. the sequence of issue id instruction is cs# goes lowsending id instructiondata out on socs# goes high. most signifcant bit (msb) frst. after the command cycle, the device will immediately output data on the falling edge of sclk. the manufacturer id, memory type, and device id data byte will be output continuously, until the cs# goes high. table 7. id defnitions rdid command manufacturer id memory type memory density c2 20 14 res command electronic id 13 rems/rems2/rems4/ command manufacturer id device id c2 13 9-23. enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. the additional 4k-bit secured otp is independent from main array, which may use to store unique serial number for system identifer. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes lowsending enso instruction to enter secured otp mode cs# goes high. please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once security otp is lock down, only read related commands are valid. 9-24. exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes lowsending exso instruction to exit secured otp modecs# goes high. mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
42 9-25. read security register (rdscur) the rdscur instruction is for reading the value of security register. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes low sending rdscur instruction security regis - ter data out on so cs# goes high. the sio[3:1] are don't care when during this mode. 2 1 345678 9 10 11 12 13 14 15 command 0 7 6543210 security register out security register out high-z msb 7 6543210 msb 7 sclk si cs# so 2b figure 25. read security register (rdscur) sequence (command 2b) the defnition of the security register is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non- factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for cus - tomer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be update any more. while it is in 4k-bit secured otp mode, main array access is not allowed. table 8. security register defnition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x ldso (indicate if lock-down secured otp indicator bit reserved reserved reserved reserved reserved reserved 0 = not lock-down 1 = lock-down (cannot program/erase otp) 0 = non-factory lock 1 = factory lock volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
43 9-26. write security register (wrscur) the wrscur instruction is for changing the values of security register bits. the wren instruction is required be - fore sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. the sio[3:1] are don't care when during this mode. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. figure 26. write security register (wrscur) sequence (command 2f) 2 1 34567 0 2f sclk si cs# command so high-z mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
44 9-27. read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is same as cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a jedec standard. jesd216. figure 27. read serial flash discoverable parameter (rdsfdp) sequence 23 2 1 3456789 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 5ah command mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
45 table 9. signature and parameter identifcation data values description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers this number is 0-based. therefore, 0 indicates 1 parameter header. 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number ( macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
46 table 10. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not suport 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction required for writing to volatile status registers 0: not required 1: required 00h to be written to the status register 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 1b f1h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support 1=support 19 0b (1-2-2) fast read 0=not support 1=support 20 1b (1-4-4) fast read 0=not support 1=support 21 1b (1-1-4) fast read 0=not support 1=support 22 1b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 007f ffffh (1-4-4) fast read number of wait states (note3) 0 0000b: wait states (dummy clocks) not support 38h 04:00 0 0100b 44h (1-4-4) fast read number of mode bits (note4) 000b: mode bits not support 07:05 010b (1-4-4) fast read opcode 39h 15:08 ebh ebh (1-1-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ah 20:16 0 1000b 08h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 6bh 6bh mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
47 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) (1-1-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ch 04:00 0 1000b 08h (1-1-2) fast read number of mode bits 000b: mode bits not support 07:05 000b (1-1-2) fast read opcode 3dh 15:08 3bh 3bh (1-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3eh 20:16 0 0100b 04h (1-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-2-2) fast read opcode 3fh 31:24 bbh bbh (2-2-2) fast read 0=not support 1=support 40h 00 0b eeh unused 03:01 111b (4-4-4) fast read 0=not support 1=support 04 0b unused 07:05 111b unused 43h:41h 31:08 ffh ffh unused 45h:44h 15:00 ffh ffh (2-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 46h 20:16 0 0000b 00h (2-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 ffh ffh (4-4-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 4ah 20:16 0 0000b 00h (4-4-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (4-4-4) fast read opcode 4bh 31:24 ffh ffh sector type 1 size sector/block size = 2^n bytes (note5) 0x00b: this sector type doesn't exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 4eh 23:16 10h 10h sector type 2 erase opcode 4fh 31:24 d8h d8h sector type 3 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 50h 07:00 00h 00h sector type 3 erase opcode 51h 15:08 ffh ffh sector type 4 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
48 table 11. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 36h 00h 36h vcc supply minimum voltage 1650h=1.650v 2250h=2.250v 2350h=2.350v 2700h=2.700v 63h:62h 23:16 31:24 00h 27h 00h 27h h/w reset# pin 0=not support 1=support 65h:64h 00 0b 4ff4h h/w hold# pin 0=not support 1=support 01 0b deep power down mode 0=not support 1=support 02 1b s/w reset 0=not support 1=support 03 0b s/w reset opcode reset enable (66h) should be issued before reset opcode 11:04 1111 1111b (ffh) program suspend/resume 0=not support 1=support 12 0b erase suspend/resume 0=not support 1=support 13 0b unused 14 1b wrap-around read mode 0=not support 1=support 15 0b wrap-around read mode opcode 66h 23:16 ffh ffh wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 ffh ffh individual block lock 0=not support 1=support 6bh:68h 00 0b cffeh individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 1b individual block lock opcode 09:02 1111 1111b individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 1b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11b unused 31:16 ffh ffh unused 6fh:6ch 31:00 ffh ffh mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
49 note 1: h/b is hexadecimal or binary. note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: wait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch,32kb=2^0fh,64kb=2^10h note 6: all unused and undefned area data is blank ffh. mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
50 10. power-on state the device is at below states when power-up: - standby mode (please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uf) mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
51 vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns 11. electrical specifications 11-1. absolute maximum ratings symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 125c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v notice: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the de - vice. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see the fgures below. figure 28. maximum negative overshoot waveform 11-2. capacitance figure 29. maximum positive overshoot waveform ta = 25c, f = 1.0 mhz mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
52 device under test diodes=in3064 or eq uiv alent cl 6.2k ohm 2.7k ohm +3.3v cl=30/15pf including jig capacitance figure 30. input test waveforms and measurement level figure 31. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
53 table 12. dc characteristics temperature = -40c to 85c for industrial grade notes : 1. typical values at vcc = 3.3v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. 3. it is measured under checkboard pattern. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 20 50 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 3 20 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 25 ma f=108mhz, ft=104mhz(vcc=3.0v~3.6v, 2 x i/o read) fq=108mhz (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 15 ma ft=80mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open 10 ma f=50mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 20 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
54 table 13. ac characteristics temperature = -40c to 85c for industrial grade notes: 1. tch + tcl must be greater than or equal to 1/ f (fc or fr). 2. value guaranteed by characterization, not 100% tested in production. 3. tshsl=15ns from read instruction, tshsl=50ns from write/erase/program instruction. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. test condition is shown as "figure 30. input test waveforms and measurement level" and "figure 31. output loading" . symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, rdsfdp, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr d.c. 108 mhz frsclk fr clock frequency for read instructions 50 mhz ftsclk ft clock frequency for 2read/dread instructions 2.7v-3.6v 80 mhz 3.0v-3.6v 104 mhz fq clock frequency for 4read/qread instructions 108 mhz f4pp clock frequency for 4pp (quad page program) 33 mhz tch(1) tclh clock high time serial 4.5 ns normal read 9 ns 4pp 14 ns tcl(1) tcll clock low time serial 4.5 ns normal read 9 ns 4pp 14 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 3 ns tchsl cs# not active hold time (relative to sclk) 3 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 2 ns tchsh cs# active hold time (relative to sclk) 3 ns tshch cs# not active setup time (relative to sclk) 3 ns tshsl(3) tcsh cs# deselect time read 15 ns write/erase/program 50 ns tshqz(2) tdis output disable time 2.7v-3.6v 9 ns 3.0v-3.6v 9 ns tclqv tv clock low to output valid loading: 30pf/15pf loading: 30pf 9 ns loading: 15pf 8 ns tclqx tho output hold time 0 ns twhsl write protect setup time 20 ns tshwl write protect hold time 100 ns tdp(2) cs# high to deep power-down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 20 us tres2(2) cs# high to standby mode with electronic signature read 20 us tw write status register cycle time 40 100 ms tbp byte-program 9 300 us tpp page program cycle time 0.7 3 ms tse sector erase cycle time 60 300 ms tbe block erase cycle time 0.4 2.2 s tce chip erase cycle time 3 15 s mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
55 figure 32. serial input timing figure 33. output timing 12. timing analysis sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv sclk so cs# si mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
56 12-1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: the parameter is characterized only. symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 300 us note: vcc (max.) is 3.6v and vcc (min.) is 2.7v. v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) table 14. power-up timing figure 34. power-up timing mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
57 notes : 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "table 13. ac characteristics" . symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v 13. operating conditions at device power-up and power-down ac timing illustrated in "figure 35. ac timing at device power-up" and "figure 36. power-down sequence" are for the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ignored, the device will not operate correctly. during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 35. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
58 figure 36. power-down sequence c s # sclk v c c during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
59 14. erase and programming performance 15. data retention min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. 16. latch-up characteristics parameter condition min. max. unit data retention 55?c 20 years notes: 1. typical program and erase time assumes the following conditions: 25 c, 3.3v, and checker board pattern. 2. under worst conditions of 85 c and 2.7v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. parameter min. typ. (1) max. (2) unit write status register cycle time 40 100 ms sector erase cycle time 60 300 ms block erase cycle time 0.4 2.2 s chip erase cycle time 3 15 s byte program time (via page program command) 9 300 us page program cycle time 0.7 3 ms erase/program cycle 100,000 cycles mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
60 17. ordering information part no. clock (mhz) temperature package remark mx25l8073em2i-10g 108 -40c~85c 8-sop (200mil) mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
61 18. part name description mx 25 l 10 m2 i g option: g: rohs compliant speed: 10: 1 i/o 108mhz, 2 i/o 80mhz, 4 i/o 108mhz temperature range: i: industrial (-40c to 85c) package: m2: 200mil 8-sop density & mode: 8073e: 8mb type: l: 3v device: 25: serial flash 8073e mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
62 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
63 19. revision history revision no. description page date 0.00 1. initial released all nov/13/2012 1.0 1. removed advanced information status p4 jan/18/2013 mx25l8073e p/n: pm1911 rev. 1.0, jan. 18, 2013
except for customized products which have been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macro - nix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2012. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provid er, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only. for the contact and order information, please visit macronixs web site at: http://www.macronix.com 64 mx25l8073e macronix international co., ltd. reserves the right to change product and specifcations without notice.

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